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PD64012 1 2-channel poe manager preliminary datasheet description __________________ powe rdsin e ?s? pd640 1 2 powe r o v er etherne t (poe) m ana ger chi p inte grate s p o wer, analo g an d logic fu nctio n s into a si ngl e 64 -pin, pl a s tic p a ck. it i s use d in ethernet swit che s and mid s pa n s to allow nex t gene ration n e twork devi c es to sh are p o we r and d a ta over the sa m e cabl e. the devi c e i s a twelve -p ort, mix-sig n a l , high-voltag e powe r over e t hernet d r iver. the poe manag er all o ws the detection of ieee 802.3af -2003 compli ant terminal s, referred to as powere d dev ice s o r pds, ensurin g saf e powe r fe eding an d removal over ethernet po rts. with full digital cont ro l via a serial comm uni cati on inte rface and a mini m u m of extern al comp one nts, the devi c e i n tegrate s i n multi-po rt an d highly popul a t ed ethernet swit che s . the pd640 1 2 implem ent s all real ti me fun c tions according to ieee 802.3af-2003, includi ng: detection, cla ssifi cation, and port sta t us monito rin g ; as well a s system level activities such as: po wer manag eme n t and mib sup port, for syst em mana ge ment. the poe manag er i s de signe d to dete c t and disa ble discon ne cted port s , u s i ng bot h dc a nd a c disconnect methods, as defined in ieee 802.3af- 2003. the pd64 012 ha s two po ssi ble working config uratio n s : an auto m ode (stan d -al one topol ogy ) for ba si c po e function s a nd a n enh a n c ed mod e fo r extended fun c tion s. pin configuration _____________ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 pd6 4012 vpe r i ext _ r eg v cc2 p 5 a s i ci ni i2 c i n i a dc2 p 5 ir ef qgn d re s e t _ n sd a sc l sc k mo s i mi s o cs 0 _ n re se rve d te s t _ m o d e re s e r v e d features ____________________ ? ieee 802.3af-2003 compli ant ? drive s 12 ind epen dent po wer p o rt s ? can b e ca sca ded for up to 48 port s , usin g a mas t er/s lave architec ture ? suppo rts ietf powe r ethernet mib (rf c 362 1) ? therm a l protection p e r po rt ? therm a l moni toring capa bil i ties ? multi-poi nt re sisto r dete c tion ? suppo rts dc modulatio n m e thod un der-curre nt detectio n accordin g to ieee 802.3af-2 0 03 ? ac & dc di sconne ct functi ons ? p d cla ssif i cat i on f unct i o n ? operates fro m single in pu t (44 to 57 v) ? i 2 c bus inte rface ? suppo rts fold back current l i miting ? digitally pro g rammabl e ove r cu rrent prote c tion per po rt ? digitally pro g rammabl e timers ? powe r mana gement alg o ri thm for up to 48 port s ? internal po we r-o n re set ? power s o ft-s t art algorithm ? fast po we r shutdo wn, in case of po we r supply failure ? automatic on/ off seque ncer for up to 48 ports ? disable/e nabl e power feedi ng ? contin uou s p o rt cu rrent monitorin g vp o r t _ n e g0 po r t _ s e n se 0 vp o r t _ n e g1 po r t _ s e n se 1 vp o r t _ n e g2 po r t _ s e n se 2 vp or t _ n e g 3 po r t _ s en s e 3 vp or t _ n e g 4 po r t _ s en s e 4 po r t _ s en s e 5 vp or t _ n e g 5 ag n d sen s e _ n eg vpo r t _ n e g 1 1 po r t _ s en se 11 vpo r t _ n e g 1 0 po r t _ s en se 10 vpo r t _ n e g 9 po r t _ s en se 9 vpo r t _ n e g 8 po r t _ s en se 8 vpo r t _ n e g 7 po r t _ s en se 7 po r t _ s en se 6 vpo r t _ n e g 6 d i sa ble _ po r t s cs 1 _ n ag n d vpor t _ p os 7 vpor t _ p os 1 vpor t _ p os 2 vpor t _ p os 3 vpor t _ p os 4 vpor t _ p os 5 vpor t _ p os 9 vpor t _ p os 10 vpor t _ p os 11 vm ain vpor t _ p os 8 cp _ i n cp _ o ut re f _ p o rt _n e g vpor t _ p os 6 vpor t _ p os 0 dg n d 042 02al1 w0 7 ? suppo rts ba ck-off feature for mid s pa n impleme n tation ? additional fea t ures fo r enh anced mod e : ? uart inte rfa c e ? pre-stand ard pd detectio n ? suppo rts no n - stan da rd terminals ? advance d po wer m ana ge ment ? programma bl e port matrix ordering information part temp. ran ge pin package pd640 12 -20 to +85 c lqfp-64 date code : see the bottom line ( 042 02a l1w07 ) in the pin confi guratio n drawing. ? 042 0 ? i s the date cod e . ? 04 ? the year (2 004 ), while ? 20 ? is the week . pow erdsine the power o v er et hern et pion eers t h is document cont ain s inf o rmat ion t hat is pr opriet a ry t o powerd sin e . as such, it is confide n tial and it s disclosure i s st rict l y prohibit ed by applicab le l a w. i f you a nd/ or your company a n d powerdsine have execut ed a non-d i sclosure agreement , t hen t h is document is bei ng provide d in co nnect i on wit h t he agreement , and t he inf o r mat i on c ont ained h e rein is cove red by t he agreement a nd under it s t e rms may not be disclo s ed or used and must b e prot ect ed by you and/or your company.
PD64012 12-channel poe manager maximum ratings ______________________________________________ v main ????? ???? ?? ? ???? ?? ? -0.3 to 80 v (1) dgn d , agnd, qgnd, sense _neg? ???.. -0.3 to 0.3 v (2) clk, resetn, cs0_n, cs1_n?.???... -0.3 to (v pe ri + 0. 3) v v port_ p osx ?? ???? ?? ? ???..? ? -0.3 to 80 v (1) v port_n egx , ref_port_ n eg v port_ p osx - v por t _neg x port_sensex ???? ?? ? ???..? ?? -0.3 to 15 v vcc 2p5 , adc 2p5 ????. ?? ? ???? ??... . -0.3 to 3 v v peri ????? ???? ??.. ???? ?? ?. 4 v ext_reg? ? ???? ?? ? ???? ?..? ? -0.3 to 6 v i2cini, asicini ???? ?? ? ???? ?? ? -0.3 to 3 v miso, mosi, s c k, scl, sda, esd (human bo dy model)?????.?.? -2 to 2 kv (3 ) max junction te mperature (t j unc )????.. ? +15 0 c junction-ambien t thermal resistance ( ja )?.. 25 c/w junction-case th ermal resistance ( jc )???16 c/w lead temperature (soldering, 10 s)????. 300 c storage tempera t ure?? ??? ???? ?..-40 to +125 c notes: ?x? define s port numbe rs, 0 thru 11, inclusive. (1) 80 v is the tr a n sient voltage that can be applied for at most one minute. (2) ma ximum value bet w een grou nds. (3) esd testing i s performed in a ccordance w i th t he human bod y model (c za p = 10 0 pf, r za p = 150 0 ? ). stresses beyond those listed above, m a y cause p e r m anent d a m ag e to the device. exposure to abs olut e m a xi m u m r a ting conditions fo r extended periods , m a y affect devi c e reliability. operating conditions ___________________________________________ paramete r min. nom. max. unit operating tempe r ature -20 +85 c operational limit ations (1) 15 to 44 44 to 55 55 to 57 v (1) operat ing f unct i ons depend on t he input volt age, as shown in t he dist ribution of fig u re 1. 15 57 44 55 com m unicat i ons (operat es ov er ent ire rang e) p ol 802. 3af com p l i ance (f rom 44 t o 57 v ) ac d i sconnect (only up t o 55 v ) v figure 1 - o p eratio nal ranges electrical characteris tics ________________________________________ dc characteristics for digital inputs and outputs paramete r symbol min. max. unit remarks pin name disable_p o r t s type schmitt trigger cmos input, ttl level with inter nal pullup high level input voltage v ih 2 . 0 v low level input voltage v il 0 . 8 v in p ut volta g e h y s t e r e s i s 0 . 3 v input high current i ih + 1 0 + 1 5 0 a input low current i il n a n a a www.powerdsine.com ? powerdsine 2003 i n f o r m ati on i n t h i s document subj ect 06-0003-058 (rev. 2. 8) / 5 august 2004 to change wi thout pr i o r noti ce. 2
PD64012 12-channel poe manager dc characteristics for digital inputs and outputs paramete r symbol min. max. unit remarks (co n tinue d) pin name scl type schmitt trigger cmos input, ttl level with inter nal pullup high level input voltage v ih 2 . 0 v low level input voltage v il 0 . 8 v in p ut volta g e h y s t e r e s i s 0 . 3 v input high current i ih n a n a a input low current i il - 1 5 0 - 1 0 a pin name mosi, miso, cs0_n, cs1_n, sck type cmos i/ o, ttl level with no inte rnal pull up/pull down resistor high level input voltage v ih 2 . 0 v low level input voltage v il 0 . 8 v in p ut volta g e h y s t e r e s i s 0.3 v input high current i ih - 1 + 1 a input low current i il - 1 + 1 a high level output voltage v peri - 0 . 4 v v i out = 3 ma low level output voltage 0.4 v i out = 3 ma tri state output current -1 +1 a pin name reset_n, sda type cmos open drai n output with schmitt trigger inp u t, ttl level high level input voltage 0.4 v i out = 3ma low level input voltage v il 0 . 8 v in p ut volta g e h y s t e r e s i s 0.3 v off state output current -1 +1 a electrical characteristics for analog i/o pads paramete r min. max. unit remarks pin name vport_p osx, vport_neg x, ref_port_ne g operating voltage 44 62 v pin current consumption -5 +5 a port driver off, v port differentia l m easurement off, ac generator off pin name port_sensex operating voltage 0 1.48 v with external 2 ohms (1 % ) to ground internal current consumption 20 a pin name vmain operating voltage 44 57 v v main current consumption 20 ma total on v main pin name cp out operating voltage 44 67 v pin current consumption 5 ma pin name adc 2p5 , vcc 2p5 , v peri , ext_reg adc 2p5 output voltage 2 . 4 5 2 . 5 5 v adc 2p5 internal current consumption 6 ma recommended external cap. = 47 to 135 nf vcc 2p5 output voltage 2.37 2.62 v recommended external cap. = 47 to 135 nf vcc 2p5 internal current consumption 5 m a v peri output volt age 3.13 3.46 v recommended external cap. = 1 to 4.7 f v peri external cu rrent load 6 ma without external npn ext_reg outpu t current 6 ma when using exte rnal npn for v pe ri www.powerdsine.com ? powerdsine 2003 i n f o r m ati on i n t h i s document subj ect 06-0003-058 (rev. 2. 8) / 5 august 2004 to change wi thout pr i o r noti ce. 3
PD64012 12-channel poe manager electrical characteristics for analog i/o pads paramete r min. max. unit remarks (co n tinue d) pin name asicini, i2ci ni operating voltage 0 adc 2p5 v current consum ption -1 +1 a pin name i ref output voltage 1.21 1.34 v with external 24 .9 k ? resistor to ground dy namic characteristics the pd6 401 2 is an adva n c ed p o wer-li miting device that us e s thre e prog ram m a b le cu rrent le vel threshold s (i min , i cut , i lim ) and two ti mers (t min , t cut ), to operat e as sho w n i n figure 2. l oad s that dissipate m o re t han i cut for longer th an t cut (ovl_s t o ovl) are cl assified a s o v erload s a n d are automati c ally shutdo wn. output p o w er di ssip a tio n belo w i min for du ring more th an t min (udl_s to udl) will be cl assified as no -l oad and will al so be shutdown. a u tomati c recovery fro m overload a nd no-l oad condition s are attempted every t ovlrec and t udlrec p e riod s (typica lly 5 and 1 se con d s, re s pect i v e ly ). i n any ca se, out put po we r is l i mited to i lim, whi c h i s a m a ximum pe ak power allo wed at the port. paramete r con d iti o ns min. typ. max. unit automatic recovery from overload shutdo wn t ovlrec value, m easured from po rt shutdown (can be modified through control port) 5 s automatic recovery from no-load shutdown t udlrec value, m easured from po rt shutdown (can be modified through control port) 1 s cutoff timer s accur a cy typical ac cur a cy of t cut 1 0 m s inr u sh cur r ent i in r s h for t=50 ms, c lo a d =180 uf max. 4 0 0 4 5 0 m a output current operating range i port continuous operation after startup period. 1 0 3 5 0 m a output power av ailable, operating range p po rt continuous operation after startup period, at port output. 0 . 5 7 1 5 . 4 w i min1 must disconne ct for t greater tha n t uvl 0 5 m a off mode curren t i min2 may or may not disconnect for t greater than t uv l 5 7 . 5 1 0 m a pd power maint enance request drop-out time limit t pmdo buffer period to handle transitions 3 0 0 4 0 0 m s over load curren t detection range i cut time limited to t ovl 3 5 0 4 0 0 m a over load time limit t ovl 5 0 7 5 m s turn on ris e tim e t ri se from 10% to 90 % of v po rt (specified for pd load consisting of 100 uf capacitor in parallel to 200 ? ). 1 5 u s turn off time toff from v port to 5 vdc 500 ms thermal data power con s umption ? th e internal p o w er con s u m p t ion of a singl e device fro m the dc inp u t is ba sed o n : input voltage rang e?? ? ? 44 to 57 vdc input cu rre nt???? ?? ? 10 ma typ.; 15 ma max. www.powerdsine.com ? powerdsine 2003 i n f o r m ati on i n t h i s document subj ect 06-0003-058 (rev. 2. 8) / 5 august 2004 to change wi thout pr i o r noti ce. 4
PD64012 12-channel poe manager p main = v ma i n x i mai n p main typ. = 48 vdc x 10 ma = 0.480 w . p main max. = 57 vdc x 15 ma = 0.855 w devic e powe r dissipa tion ? the pd640 12 incorp orates 12 p o wer mosfets, e a ch cha r a c terized by: re sista n ce from drai n-sou r ce r ds(on) = 0.3 ? typ. ; 0.5 ? max. drai n-so urce curre n t i ds = 360 ma max. maximum po wer di ssipatio n p mosfet max. of a single pd6401 2 de vice (for 1 2 m o sfets) : [(i ds ) 2 x r ds(on) ] x 12 = [(0.36 a) 2 x 0.5 ? ] x 12 = 0.78 w cha r ge p u mp (see an alog section of block dia g ra m de scription, h e reafte r) po wer dissip ation p cp is 0.21 w. total power d i ssi pation p total by device, under m a ximu m conditio n s: p total = p ma in max . + p m o sf et max. + p cp = 0.855 w + 0.78 w + 0.2 1 w = 1.84 5 w i li m i cu t i min t min udl _ s ud l po rt of f ov l t cu t ov l_ s i ch an n e l po r t 1 po r t 2 figure 2: po w e r limits protection mechanism the pd6 401 2 inclu d e s internal th erm a l prote c tion to avoi d junctio n overh eat. three type s of temperatu r e sen s o r s are integ r ate d into the device: two a r e u s ed fo r prote c tion and on e for tempe r atu r e monitori ng. hi-temp pro t ec tion ? th e device co n t ains the r mal shutd o wn s. this p r ote c ti on sy stem is activated in extreme conditions. lo-temp pro t ec tion ? there are the r m a l sen s o r s th at are intend ed to protect the function ality of the device, in ca se s of temperatu r e ri se. indicator se nsors ? fou r temperature sen s o r s moni tor the l o cal te mpe r ature i n the d e vice. thei r ave r ag e is also cal c ulate d by the pd640 1 2 . all value s are sto r ed i n intern al regis t ers for data retrieva l. th e re giste r val ues are cal c ulate d by: de cimal valu e = 684 - 1.5 14 x [(t junc )+ 40 c]. www.powerdsine.com ? powerdsine 2003 i n f o r m ati on i n t h i s document subj ect 06-0003-058 (rev. 2. 8) / 5 august 2004 to change wi thout pr i o r noti ce. 5
PD64012 12-channel poe manager pins description s ______________________________________________ pin pin name pin type pin descripti o n 1. v port_ p os0 analog i/o port 0 positive voltage feeding 2. v port_ p os1 analog i/o port 1 positive voltage feeding 3. v port_ p os2 analog i/o port 2 positive voltage feeding 4. v port_ p os3 analog i/o port 3 positive voltage feeding 5. v port_ p os4 analog i/o port 4 positive voltage feeding 6. v port_ p os5 analog i/o port 5 positive voltage feeding 7. v port_ p os6 analog i/o port 6 positive voltage feeding 8. v port_ p os7 analog i/o port 7 positive voltage feeding 9. v port_ p os8 analog i/o port 8 positive voltage feeding 10. v port_ p os9 analog i/o port 9 positive voltage feeding 11. v p o r t _p o s 10 analog i/o port 10 positive voltage feeding 12. v p o r t _p o s 11 analog i/o port 11 positive voltage feeding 13. v main supply main voltage su pply 14. cp_in analog i/o charge pump input, 48v+5v 15. cp_out analog i/o charge pump p u lse output 16. ref_port_ne g analog i/o port negative reference 17. test_m ode analog i/o test mode pin (connect to ground) 18. v port_n eg1 1 analog i/o port 11 negative voltage feeding 19. a g n d s u p p l y a n a l o g g r o u n d 20. port_sense1 1 analog i/o channel current monitoring 21. v port_n eg1 0 analog i/o port 10 negative voltage feeding 22. port_sense1 0 analog i/o channel current monitoring 23. v port_n eg9 analog i/o port 9 negative voltage feeding 24. port_sense9 analog i/o channel current monitoring 25. port_sense8 analog i/o channel current monitoring 26. v port_n eg8 analog i/o port 8 negative voltage feeding 27. port_sense7 analog i/o channel current monitoring 28. v port_n eg7 analog i/o port 7 negative voltage feeding 29. port_sense6 analog i/o channel current monitoring 30. disable_ports _ n digital input disable all ports power (active low) 31. v port_n eg6 analog i/o port 6 negative voltage feeding 32. cs1_n digital i/o spi bus, chip select 1 33. d g n d s u p p l y d i g i t a l g r o u n d 34. cs0_n digital i/o spi bus, chip select 0 35. miso digital i/o spi bus, master in/slave out 36. mosi digital i/o spi bus, master out/slave in 37. sck digital input spi bus, serial clock i/o 38. scl digital input i2c bus, serial clock input 39. sda digital i/o i2c bus, open drain 40. reset_n digital i/o active low rese t i/o 41. i r e f a n a l o g i / o c u r r e n t referenc e 42. asicini analog input analog input for asic initializatio n 43. vcc 2p5 supply internal 2.5 v supply (do not use! ) 44. i2cini analog input analog input for i2c initialization 45. qgnd supply quiet analog ground 46. adc 2p5 supply adc refe rence (do not use!) 47. ext_reg analog out external regulation 48. v peri analog out regulated 3.3 v power source 49. reserved digital input (connect to grou nd) 50. v port_n eg5 analog i/o port 5 negative voltage feeding www.powerdsine.com ? powerdsine 2003 i n f o r m ati on i n t h i s document subj ect 06-0003-058 (rev. 2. 8) / 5 august 2004 to change wi thout pr i o r noti ce. 6
PD64012 12-channel poe manager pin pin name pin type pin descripti o n 51. a g n d s u p p l y a n a l o g g r o u n d 52. port_sense5 analog i/o channel current monitoring 53. v port_n eg4 analog i/o port 4 negative voltage feeding 54. port_sense4 analog i/o channel current monitoring 55. v port_n eg3 analog i/o port 3 negative voltage feeding 56. port_sense3 analog i/o channel current monitoring 57. port_sense2 analog i/o channel current monitoring 58. v port_n eg2 analog i/o port 2 negative voltage feeding 59. port_sense1 analog i/o channel current monitoring 60. v port_n eg1 analog i/o port 1 negative voltage feeding 61. port_sense0 analog i/o channel current monitoring 62. sense_neg analog i/o port sense reference 63. v port_n eg0 analog i/o port 0 negative voltage feeding 64. r e s e r v e d t b d not c o n n e c t e d functional description ________ operational modes the pd640 1 2 su ppo rts two main m ode s of op eratio n , based o n two differe nt a r chite c tu re s, as d e scribed here a fter. t h e two mo de s are: enh a n c ed m ode and automatic mode. enhan ced m ode ? in t h is mo de of o peratio n, the pd640 12 s communi cate with the pd630 00 p o e mcu (de d icated mcu for power o v er ethern e t task s ) , throu gh a serial p a rallel inte rfa c e (spi) bu s. in this mod e , all p d 64 012 s a r e di re ctly co nne cted t o the pd630 00 through the spi, in slave mode. the mcu is use d for a dditio nal power o v er ethernet feature s , su ch as: ? lega cy pds detectio n (in c luding cisco discovery ) ? enhan ced p o w er m ana ge ment algo rith ms ? led indi cato rs su ppo rt ? port matrix control ? comm uni cati on proto c ol transl a tor. the switch host cpu commu nica tes with th e pd630 00, via an isolated i 2 c or ua rt b u s, as s h o w n in figure 3. pd 6 4 0 1 2 #00 pd 6 4 0 1 2 #01 pd 6 4 0 1 2 #10 pd 6 4 0 1 2 #11 mi so sc k mo si i/o o p t o ho s t cpu cs0 _ n cs1 _ n cs0 _ n cs1 _ n cs0 _ n cs1 _ n cs0 _ n cs1 _ n cs3 cs2 cs1 cs0 i 2 c o r u a rt spi bus pd 630 00 poe m c u pul l - d ow n r e si st o r figure 3: en hance d mod e www.powerdsine.com ? powerdsine 2003 i n f o r m ati on i n t h i s document subj ect 06-0003-058 (rev. 2. 8) / 5 august 2004 to change wi thout pr i o r noti ce. 7
PD64012 12-channel poe manager automatic mode ? in this mode the p d 64 012 poe manag ers co mmuni cate with the ho st cpu, th roug h an isol ated i 2 c bus. th e pd640 12 spi bus is dedi cated f o r internal commu nication amon g pd640 12 s (for power ma nagem ent), a s illu strate d i n figure 4. ho s t cpu sda sc l sda sc l sda sc l sda sc l sda sc l i n put op to i/o o p to i 2 c bus pd 6 4012 #00 pd 6 4012 #01 pd 6 4012 #10 pd 6 4012 #11 ma s t e r sl a v e sl a v e sl a v e spi bus mo s i mi s o mo s i mi s o mo s i mi s o mo s i mi s o sck sck sck sck c s [0:1] _ n anyone of th e devices (fo r exampl e, pd64 012 #00 ) may be co nfigure d a s ma ster, while th e others are slaves. this maste r /slave configu r atio n only affects the serial pe riphe ral interf ace (spi) bu s. it is critical that only o ne of them b e set-up as a m a ster, with t h e others actin g as slave s , i n o r de r to av oid spi clock and data i/os contentio ns. figure 4: au tomatic mo d e mode configuration method the poe man ager? s config uration i s don e via the asic_ini pin, a c cording to the following tabl e. the asic_ini analog si gn al is co nverte d into a 10-bit regist e r (a/d). once a hard re set pul se is detecte d, the data is latch ed into an internal m ode re giste r . mode nam e asic_ini voltage level asic_ini int e rn al a/ d register i 2 c 2 lsb address (set internally ) enhan ced m ode 0.31 to 0.63 v 001 00 auto mode ? slave 1 0.63 to 0.94 v 010 01 auto mode ? slave 2 0.94 to 1.25 v 011 10 auto mode ? slave 3 1.25 to 1.56 v 100 11 auto mode - maste r 2.19 to 2.5 v 111 00 notes: in the auto mode ? the pd6401 2 is communicating w i th th e host via i 2 c. in the enhanced mode ? the pd 6 4012 is communicating w i th the c ontroller via spi. block diagram description (se e figu re 5) the pd64002 poe manager co mplies with all requi rements of ieee st andard 802.3af-2003, for detection. the device h a s b een de sig ned aroun d two major se ction s : 1. a common di gital se ction, that serve s all 12 cha nnel s 2. twelve sepa rate and ide n tical chan nel s for drivin g port s . www.powerdsine.com ? powerdsine 2003 i n f o r m ati on i n t h i s document subj ect 06-0003-058 (rev. 2. 8) / 5 august 2004 to change wi thout pr i o r noti ce. 8
PD64012 12-channel poe manager vp o r t m e a s u r em en t i cl a s s re g pol se q u e n c e r p o w e r m a n a ge m e nt i li m re g cu r r e n t a n d a c vo l t a g e m e asu r e m e nt ch a n n e l rt co n t r o l st a t u s o v e r lo a d / d i sco nn ec t r eco v e r y co m i n t e r f ace sp i i 2 c ov e r l o a d lo gi c dc di s c o n n e c t lo gi c a c d i sc on ne ct ma c r o c l a ssi f i ca t i o n r e si s t or li ne d e t ect i o n re a l t i m e p r ot ect i o n 8- b i t ad c i lim 8- b i t d a c i cl a s s 8- b i t d a c c u r r e n t l i m i tin g x12 cl o c k o s c illa to r vm a i n vm a i n 48 + 5 v pu m p up po r vo l t a g e re g u l a t o r r ese t + 4 8 v v p ort p os vp o r tne g po rt se ns e v p o r t l e v e l s h i fte r l i n e d e te c t io n x1 2 a c d i sc on ne ct g e ne r a t o r x1 2 ac d a c 8- b i t ld d a c vpo r t 10 - b i t ad c se n s e re s i s t o r c l as si f i cat i o n v m ai n - 1 7 v di g i t a l di g i t a l an a l o g an a l o g mi s o mo s i ss sc k sc l sd a d c d i sc on nec t co m p a r a t o r sp i i 2 c c o mmu n i c a t i o n i/o figure 5: internal bloc k diagram digital section communica tion i/o the pd6 401 2 inco rpo r ate s two commu nicatio n interf ace s . wh en o peratin g in the enhan ced mode, an spi bus con n e c ts the pd630 00 m c u to the pd6 4012 s. the seco nd interfa c e is the i 2 c, us ed in the automatic mode (with the host ) . both interfaces are used to comm uni ca te the content s of internal registe r s b e tw een the pd6 4 012 logi c an d the mcu. poe sequencer this central b l ock of the di gital se ction i n clu d e s a co mbi nation of i n ternal state machi n e s (m acros). it is fed from the overloa d /disco nne ct recove ry circ ui t and from the powe r man ageme n t block. po w e r man a gement re ceive s dat a from the vp ort mea s ure m ent block a nd re ceive s comman d s a n d controls fro m the comm unication interface. this, in orde r to control the po wer all o cate d to the system, as defined by the host. powe r mana gement receives req u e sts to en abl e ports and d e cid e s, by co mm uni cating with the sequ encer, wh eth e r po we r is to be allocated. ov erload /disconn ect re cov e r y there is a nu mber of ma cros which de ci de on po rt en able an d som e on port di sconne ct. port enabli n g : classificatio n , resi stor li ne dete ction and vpo r t measu r em ent. port disa ble : ac disco nne ct, dc di scon nect an d ove r load l ogi c. these macro s are conn ecte d to the chan nel rt control status blo ck. ba se d on the input s from the s e ma cro s , the cha nnel rt controlle r sta r ts the sh utdo wn operation o r the re cove ry process. th i s is don e acco rding to pre p rogra mmed p a ram e ters for different time wind ows, as sho w n in fig u re 2, power limits. www.powerdsine.com ? powerdsine 2003 i n f o r m ati on i n t h i s document subj ect 06-0003-058 (rev. 2. 8) / 5 august 2004 to change wi thout pr i o r noti ce. 9
PD64012 12-channel poe manager macros (80 2 .3 standa rd) cla ssif i cat i on ? upon requ est from the mcu, a state machi ne ap plies a reg u l a ted 18 v on the port out put. the internal curre n t is m e a s ured by a mete ring ci rcuit, compa r ed with a n u mbe r of pre s et ran g e s a nd in this manne r, the cla ssifi cat i on is e s tabli s hed. line dete ctio n ? the mcu gene rate s a requ est to ha ve four sep a rate voltage le vels ap plied t o the o u tput port. a uniqu e me asurem ent ci rcuit monitors t he delta bet wee n the se con d an d third levels, and betwe en th e third a n d fourth level s . the voltage differen c e s a r e compa r e d with va lue s stored in regi sters. by com parin g the va lues, the system can d e cid e wh ethe r or not to en able the po rt. ac d i s c o n nec t ? the syste m applie s a sinusoidal sign al to the po sit i ve terminal o f the port. th e voltage d e velope d on the port te rminal s i s p r o portion al to th e value of th e l oad. if the lo ad is high, th e ac com pon ent ridi ng o n the po rt terminal s, will be small an d reversed. if the load low, t he ac compone nt will be large. a sp ecial ci rcuit measures the level of the ac com pon ent and comp are s it with a val ue stored i n a regi ster. based o n the compa r i s on result s, the system d e cid e s to di sa ble the port o r not. dc di sc onn e c t for dc m o dulation : sen s e s if the po rt cu rre nt falls belo w 7.5 ma . if so, a flag i s raise d an d t i mers in the cha nnel rt controller are e nable d . the chan ne l rt c ontroll er a c ts a c cording to p r e-p r og ramm ed li mits fo r threshold s a n d time wi ndo ws, p r io r to i n itiating a di scon ne ct s t atus for that port. the c i rcuitry tak e s into acc o unt pd?s that mo dulate their curr ent co nsu m ption, disco nne cting the m only if necessary. analog section clock oscillator a 4 mhz o scil l ator, use d for internal logi c and timers. po w e r on re set (por ) monitors the i n ternal reg u la ted +3.3 v an d gene rate s a re set sign al, if this value drop s belo w 2. 8 v. the reset s i gnal res e ts the asic?s lo gic and generates an output flag to the ot her PD64012 asics , via th e reset_n pin. charg e pum p this circuit bl ock ge nerate s a voltage whi c h in crea ses t he m a in i nput voltage by 10 vd c (approx.). thi s pote n tial is used to op erate the ac disco nne ct ci rcuit s . curre nt limit this ci rcuit continuo usly checks the cu rre nt for ena bled po rts. once the cu rrent exce ed s a spe c ific le vel, the system start s to measu r e t he elap se d time. if this period i s greate r than a p r e s et threshol d, the port is disabled. in all cases, the output cu rrent will not exceed a pr e-established maxi mum. real time protec tion this ci rcuit receive s fla g s from two lo cations in th e pd 6 4012: from the sen s e resi stor an d from the m a in in put voltage (48 v ) . a 10 -bit a/ d conve r ter feed s the di gital sectio n, at the current a nd a c voltag e me asu r em e n t blo c k. from the r e o n , the system handle s the l e vels a c cordi ng to pre - pro g ramm ed limi t s. dc discon n ect compara t or once the port current d r op s belo w a set limit, the comparato r provides a n indi ca tion to the dc discon ne ct logic to that effec t. pd-im-7348 evaluation board the pe rform a nce featu r e s of the pd640 12 poe mana ger can be ful l y appre c iate d with the pd-im-73 48 eva l uation board. thi s b oard all o ws to investigate all function s a c cessibl e to the de sign er. the evaluatio n board su pp orts up to 48 port s , has both i 2 c a nd uart inte rface s an d ca n demon strate the enhan ced and auto mode s. www.powerdsine.com ? powerdsine 2003 i n f o r m ati on i n t h i s document subj ect 06-0003-058 (rev. 2. 8) / 5 august 2004 to change wi thout pr i o r noti ce. 10
PD64012 12-channel poe manager i 2 c interface a standa rd i 2 c interfa c e is use d to com m unicate bet wee n the pd6401 2 and th e host control l er. the pd6 401 2?s i 2 c interfa c e is d e si gne d to supp ort the followi ng feature s : ? slave mode only ? normal-mod e and fa st-mo de data rate (0 to 400 kb/ s ) ? 7-bit add re ssi ng - the 7-bit addressin g (1 28 add re sses) use s the foll owin g add re ss co de: ? first msb = ?0? (fo r ced by internal lo gic) ? 4 msb addre ss bit s are se t via the i2c_ini pin, according to the followin g table ? ? mm ? bits are set throu gh the asic_ini pin (enh an ce d mode = ?00 ? ; automatic mode ma ster =?0 0 ?; autom a tic mode sla v e = ?01 ? , ?10 ? , ?11 ?) ? ? xxx ? - 3 lsb are igno re d. i 2 c ad dres s i2c_ini voltage level i2c_ini inte rn al a/ d r e gister notes addre s s #0 0 to 0.15 v 0,0000, mm,x x x addre s s #1 0.16 to 0.31 v 0,0001, mm,x x x addre s s #2 0.32 to 0.47 v 0,0010, mm,x x x addre s s #3 0.48 to 0.62 v 0,0011, mm,x x x general call addresses; not to be used addre s s #4 0.63 to 0.77 v 0,0100, mm,x x x addre s s #5 0.78 to 0.93 v 0,0101, mm,x x x addre s s #6 0.94 to 1.09 v 0,0110, mm,x x x addre s s #7 1.10 to 1.24 v 0,0111, mm,x x x addre s s #8 1.25 to 1.40 v 0,1000, mm,x x x addre s s #9 1.41 to 1.55 v 0,1001, mm,x x x addre s s #10 1.56 to 1.71 v 0,1010, mm,x x x addre s s #11 1.72 to 1.87 0,1011, mm,x x x addre s s #12 1.88 to 2.02 v 0,1100, mm,x x x addre s s #13 2.03 to 2.18 v 0,1101, mm,x x x addre s s #14 2.19 to 2.33 v 0,1110, mm,x x x addre s s #15 2.34 to 2.5 v 1,1111, mm,x x x www.powerdsine.com ? powerdsine 2003 i n f o r m ati on i n t h i s document subj ect 06-0003-058 (rev. 2. 8) / 5 august 2004 to change wi thout pr i o r noti ce. 11
PD64012 12-channel poe manager package information the pd6 401 2 is hou se d in a 64-pi n pla s tic pa ckag e, 10 x 10 x 1.4 mm, meeting je de c?s ms-026 pa ckag e outline and dime nsi o ns. expose d pad (fo r heat-sin king p u rp o s e s ) dim e n s i ons a r e 6.00 by 7.00 mm. d/ 2 e1/ 2 e/ 2 d1 d e1 e 4 p l s pin 1 i d en t i f i er 64 49 48 33 32 17 16 1 7 0. 2 h a- b d 0. 2 c a- b d vie w y b a d d1/ 2 d not e s : 1. dim ens i ons are in m ill im et ers . 2. i n t e r p r e t di m ens ions an d to leranc es pe r a s m e y 14. 5m - 1 994. 3. dat u m s a , b an d d t o be de term ined at dat um plane h. 4. dim ens i ons d and e t o be det erm i ned at s eat ing plane c. 5. dim ens i on b does not inc l ude dam bar prot r u s i on. a l l o w abl e dam b a r prot rus i on s hall not c aus e t he lead w i dt h t o ex c eed t he m a x i m u m b d i m ens ion by m o re t han 0. 08 m m . dam b ar c annot be loc a te d on th e low e r radiu s or t he f oot . m i nim u m s pac e b e t w een prot rus i on a nd adjac ent l ead or prot r u s i on 0. 07m m . 6. dim ens i ons d1 and e 1 do not in c l ude m o ld prot r u s i on. a l l o w a b l e prot r u s i on i s 0. 25m m per s i de . d1 and e 1 ar e m a x i m u m plas t i c body s i ze dim ens i ons inc l udi ng m o l d m i s m at c h . 7. e x ac t s hape o f ea c h c o rner is opt i onal. 8. the s e dim ens i ons appl y t o t he f l at s e c t i on of t he lead be tw een 0. 10m m and 0. 25 m m from t he lead ti p . 13 13 --- 7 7. 00 7.00 --- --- --- 0. 75 0 11 11 6. 00 0 0.20 6. 0 0 0. 08 0.08 1.00 re f. 0. 45 l1 r1 r2 f s z g z3 z2 z1 l 0. 1 5 1.45 0. 2 7 0. 2 3 0. 2 0 0. 1 6 1. 60 0. 0 5 1. 3 5 0. 17 0. 09 0. 17 12. 0 0 b s c 10. 00 b s c 0. 09 12.00 b s c 0 . 50 bsc 10.00 b s c --- d1 e e c1 e1 d b1 c b a a2 a1 dim . m i n . ma x . d i m . mi n . m a x . 0. 05 z a1 a2 (s ) l (l 1) r r1 vi e w a a ga g e pl a n e 0. 25 se a t in g pl a n e z2 (x4) z3 (x4) a b ( x 64) 0. 08 c vie w a a c h j j 0. 08 c a-b d e ( x 60) x = a,b o r d ab ab e/2 view y x b b1 c 1 c 8 secti on ab - a b bas e me ta l pla t i n g r o tate d 9 0 cw f g ex p o s e d pa d vi e w j- j figure 6: pd6401 2 mech anical dime nsions www.powerdsine.com ? powerdsine 2003 i n f o r m ati on i n t h i s document subj ect 06-0003-058 (rev. 2. 8) / 5 august 2004 to change wi thout pr i o r noti ce. 12
PD64012 12-channel poe manager applications the pd6 401 2 may be integrated into a numbe r of ap plicatio ns , ra nging fro m da ughter b o a r d s to full integration into ethernet swit che s . exampl es of su ch a p p licatio ns a r e : integrated di rectly in a swit ch ? facilitates the entire p o e concept, by includi ng the asic(s) on the main switch pcb. dau ghter b o a r d add -o n ? in whi c h the asic is integra t ed into a sm a ll pcb for poe, mounted on top of the swit ch? s main pcb. midsp an unit s ? stan d alo ne devices, in stalled b e twe en the ethern e t switch and powere d devi c e s (telep hon e, came ra, wi rel e ss lan, etc. .). these mi d s pa n units in cl ude the pd6 4012 asic a s a poe cont rol element, to inject power ove r the comm uni ca tion lines. figures 7 thru 10 provid e detailed sche matic diag ra ms for vari ou s appli c atio ns of the pd640 12. to opt o c o uple r s r5 r6 r7 r8 vp eri mi s o sck cs _ 0 cs _ 1 mo s i vmain ex _r eg res e t sd a sc l d i sa b l e_ po r t s vper i 10 0n 45 . 3 k 2r vport_ po s _ 1 vpor t_ n e g_1 vport_ po s vpor t_ n e g vpo r t_ sense vport_ po s vpor t_ n e g vpo r t_ sense vport_ po s _ 1 2 vpor t_ ne g_1 2 x1 2 x1 2 +48 v m a i n vp er i se n s e_ n e g sp i co mmu ni ca t i o n bus r1 r2 r3 r4 as i c _ i n i i2 c _ in i ad c 2 p 5 figure 7 - single-por t ap plication w i th ac discon n ect supp or t vma i n ex_ r eg re f _ por t _n e g vp e r i 100 n vc c 2 p5 a dc2p 5 ir ef vm a i n 3. 3v ( v p e ri ) 4. 7u 10 0n 10 0n 10 0n 1u 45. 3k 22.6k 47 n 10 0n cp_in cp_o u t 24 . 9 k 2. 5v figure 8 - t y pical po w e r filtering www.powerdsine.com ? powerdsine 2003 i n f o r m ati on i n t h i s document subj ect 06-0003-058 (rev. 2. 8) / 5 august 2004 to change wi thout pr i o r noti ce. 13
PD64012 12-channel poe manager r5 r6 vper i mi s o sc k mo s i vm a i n r1 r2 e x_reg as i c _ i n i i2 c _ i n i re se t d i sa b l e_ po r t s _ n vp e r i 22 0n 45 .3 k 2r vp o r t _ po s _ 1 v por t _ ne g _ 1 vp o r t _ po s vp o r t _ n e g vp o r t _ sen s e vp o r t _ po s vp o r t _ n e g vp o r t _ sen s e v p o r t _ p o s_ 12 v p ort_ ne g_ 1 2 x12 x1 2 +4 8vm a i n vper i 3 . 3v r ese t d i sa b l e_ p o r t s _ n se n s e_ n e g ad c 2 p 5 cs _ 1 mi s o sc k mo s i cs _ 1 cs _ 0 cs _ 0 r ese t d i sa b l e_ p o r t s _ n mi s o sc k mo s i cs _ 1 cs _ 0 mi s o sc k mo s i re set disa b l e_ po r t s cs_ 1_1 cs_ 1_2 cs_ 1_3 cs_ 1_4 vpe r i 3. 3v dg nd dg nd op to isolators i 2 c o r ua r t ho s t c p u dg nd p d - 6 40 12 #0 0 p d - 6 40 12 #0 1 p d - 6 40 12 #1 1 mc 9s08 1u 10 0n (pd - 64 01 2 #1 0) figure 9 - en hance d mod e applica t ion to opto r5 r6 r7 r8 vp e r i mi s o sc k cs _0 cs _1 mo s i vma i n r1 r2 r3 r4 e x_reg as i c _ i n i i2c_i n i reset sd a sc l disabl e_p ort s_n vpe r i 220n 45.3k 2r v por t_pos_1 vport _ n e g_1 v port _ pos vport _ n e g vport _ sense v port _ pos vport _ n e g vport _ sense v por t_p o s_12 v por t_n e g_12 x1 2 x12 +48v m a i n v p e ri 3.3v mi s o sc k cs _0 cs _1 mo s i reset sd a sc l disabl e_p ort s_n mi s o sc k cs _0 cs _1 mo s i reset sd a sc l disabl e_p ort s_n s e nse_neg a dc2p 5 #00 ma ster #10 s l ave #1 1 s l ave figure 10 - automa tic mo de applica t ion www.powerdsine.com ? powerdsine 2003 i n f o r m ati on i n t h i s document subj ect 06-0003-058 (rev. 2. 8) / 5 august 2004 to change wi thout pr i o r noti ce. 14
PD64012 12-channel poe manager reader notes www.powerdsine.com ? powerdsine 2003 i n f o r m ati on i n t h i s document subj ect 06-0003-058 (rev. 2. 8) / 5 august 2004 to change wi thout pr i o r noti ce. 15
PD64012 12-channel poe manager notice ________________________ ________________________________ powerdsine assum e s no responsibility or liabili ty arising from the use of this data sheet, as described herei n, nor does it c o n vey an y license u nder it s pat ent right s or t he right s of ot hers. the inf o rmat ion con t ained herein is believed t o be accurat e and re liable at t he t i me of print i ng. however, due t o on going produ ct impro v ement s and revisio n s, powerdsine cannot accept responsibility for i nadvertent e rrors , inaccuracies, subse quent change s or omissions of printed materi al. powerdsine lt d. reserves t he right t o ma ke chang es t o produ ct s and t o t heir specif icat ions as describe d in t h is document , at an y t i me, wit hout prior not ice. no rights t o any powerdsine lt d. i n t e llect ual propert y are licensed t o any thir d part y , direct ly, b y implicat ion or by any ot her met hod. covered under one or more of t he f o llowing pat ent s: 6, 643, 566; 6, 473, 608. no use with li fe-suppor t or cr itical applicati o ns _____________________________________________________________________ power d sine?s pr odu ct s ar e not designed, int ended, or aut horized f o r use as component s in syst ems int ended f o r : (1) surgical implant int o t he body, or ot her applicat ions int ended to support or sust ain lif e , or (2) any ot her applicat ion s whereby a f a ilure o f t he powerdsine?s pr oduct could creat e a sit uat ion w here personal injury, deat h or d amage t o per son s , syst ems, dat a or busi ness may o ccur . powerdsine assume s no liabilit y in connect i on wit h use in t hese sit uat ions and t he disclaimers pr ovided below in t h is manual sh all apply. should a buyer purchase or use powerdsine?s produ ct s f o r any such unint ended use or unaut horized applicat ions, buyer s hall indemnify powerdsine and it s of f i ce rs and emplo y ees against any an d all claims arising out of o r in connect i on wit h any claim of personal in jury, deat h or ot her damage of t he t y pe described above, asso ciat e d wit h such use. disclai m ers __________________________________________________________________________________________________ po werdsine makes no warranty , representati o n or g u ar antee reg a rding the suitabi lity of the pro d ucts co ntained herein fo r a n y particular purpo se, nor do es po we rdsine assume any liabili ty arising out o f the application or use of a n y pr od ucts or ci rcui t, and specific all y dis c lai m s an y an a ll liability , i ncludi ng, without limi tatio n , conse q uential or i ncidental da mag es. b y usi n g o ur pro d ucts user a g rees not to make any claim fo r punitive dama ges. po werdsine makes no re presentati on or warra nty , expresse d or implied, with respect to the suffi ciency o r accurac y or utility of an y in formati o n con t ained he rein. powe rdsine expre ssl y advises that an y use of or reliance up on said inf o r m ation is a t the risk of t h e user and that p o werdsine shall no t be liable fo r a n y damage or in jur y in cur red b y an y per son or orga nizati on arisi n g out of th e sufficien c y , accurac y , or utili t y of an y i n f o r m ation c o nta i ned herein or in c o nnec t i o n wi th the use o f any o f the pr oduc t s described herein. po werdsine i s no t responsible fo r a n y chang es in the specif ica t io ns o r errata of this p r o d uct. info rmatio n o n the basic pro d uct can be fo und at mo to ro la' s ho mepag e. revision histor y revision level / dat e para. af f e ct ed/ page descript i on 2. 3 / 10 dec. 03 ordering i n f o rmat ion/ page 1 lower t e mperat ure range delet ed. rema ins single range only: -20 t o +85 c. 2. 4 / 18 dec. 03 mode conf igurat ion met hod/ page 8 i 2 c i n t e rf ace/ page 11 delet ed ext r eneous values f o r asi c_i n i and delet ed def ault mode value. delet ed primary def a u lt value in t he t able column f o r not e s. 2. 41 / 10 jan. 04 feat ures/ page 1 changed mi b f r om d r af t t o rfc 3621. 2. 5 / 9 feb. 04 front & back pages a dded policy st at ement s and disclaimers. 2. 6 / 10 ma r. 04 several added t e mp. of jun c t i on-case, under m a x rat i ngs; added t her mal dat a on page 4; added prot ect i on mechanism on page 5. 2. 7 / 1 aug. 04 macros/ page 8 analog sect ion/ page 9 correct ed inacuracies in descript i ons. 2. 8 / 5 aug. 04 pin conf igurat ion/ 1 a dded part number and asso ciat ed desc r ipt i on. ? 2003 po w e rdsine ltd. all rights reserved. powerdsine is a registered tr ade mark of po w e r d sine ltd. all other product s or tradema r ks are pro pert y of th eir respective owners. the pro duct des cribed b y this ma nual is a licensed product of po we rdsine. www.powerdsine.com ? powerdsine 2003 i n f o r m ati on i n t h i s document subj ect 06-0003-058 (rev. 2. 8) / 5 august 2004 to change wi thout pr i o r noti ce. 16

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